BlockRAM (BRAM) Simulator

To test and debug the hwdbg effectively, a BlockRAM simulator module was developed, filled with sample testing data from a file. As the Chisel language does not directly support BlockRAM components, despite its support for SRAM modules, an 8 KB flip-flop module was created to simulate the behavior of BlockRAM. At the moment 8 KB was proved to be enough to support most of the hwdbg tasks. This module features input/output ports similar to those of Xilinx FPGA BlockRAMs, ensuring compatibility and accurate simulation. The delay characteristics of the BlockRAM were also emulated which allows the testing module to initialize the flip-flops with test data sent from the PS to PL.

In the simulation, the first half of the BlockRAM is dedicated to buffers for data transfer from PS to PL, while the second half is reserved for data transfer from PL to PS. The BlockRAM is divided into two halves to ensure that both the PL and PS do not simultaneously overwrite each other's buffer. During execution, the testing module initializes the flip-flops with test data, simulating the conditions of actual hardware interactions. After the debugger completes its operations, the second half of the BlockRAM is filled with the output data generated by the PL.

To verify the functionality and correctness of the hwdbg, the data in the BlockRAM is displayed and written to a file post-execution. This data is then interpreted based on the communication protocol, with each field's value being shown and separated for clarity. The simulation was executed using cocotb, with Verilator and Icarus serving as the backend tools. This comprehensive testing framework not only validates the hwdbg but also provides insights into the communication and data handling processes.

The following listing is an example of PS/PL shared BlockRAM contents shown in the BRAM simulator.

Number of clock cycles spent in debuggee (PL): 0
Number of clock cycles spent in debuggee (PL): 10
Number of clock cycles spent in debuggee (PL): 20
Debuggee (PL) interrupted Debugger (PS)
===============================
Content of BRAM after emulation:
Address of PL to PS communication: mem_128

PS to PL area:
mem_0:   00000000   | Checksum
mem_1:   00000000   | Checksum
mem_2:   52444247   | Indicator
mem_3:   48595045   | Indicator
mem_4:   00000004   | TypeOfThePacket
mem_5:   00000002   | RequestedActionOfThePacket
mem_6:   00000000   | Start of Optional Data
mem_7:   00000000
...

PL to PS area:
mem_128: 00000000   | Checksum
mem_129: 00000000   | Checksum
mem_130: 52444247   | Indicator
mem_131: 48595045   | Indicator
mem_132: 00000005   | TypeOfThePacket
mem_133: 00000003   | RequestedActionOfThePacket
mem_134: 00000003   | Start of Optional Data
mem_135: 0000000c
mem_136: 00000009
mem_137: 0000000b
mem_138: 00000000
...